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/Title (MC68HC908AZ60A, MC68HC908AS60A, MC68HC908AZ60E - Data Sheet)
/Author ( Freescale Semiconductor, Inc.)
/Subject (The MC68HC908AS60A, MC68HC908AZ60A, and MC68HC908AZ60E are members of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units \(MCUs\). All MCUs in the family use the enhanced M68HC08 central processor unit \(CPU08\) and are available with a variety of modules, memory sizes and types, and package types. These parts are designed to emulate the MC68HC08ASxx and MC68HC08AZxx automotive families and may offer extra features.)
/Keywords (MC68HC908AZ60A, MC68HC908AS60A, MC68HC908AZ60E, M68HC08 Family, CPU08, emulate the MC68HC08ASxx and MC68HC08AZxx automotive families)
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Acrobat Distiller 7.0.5 (Windows)
2006
2006-05-10T11:24:43Z
FrameMaker 7.0
2006-05-11T11:14:47-05:00
2006-05-11T11:14:47-05:00
application/pdf
Freescale Semiconductor, Inc.
The MC68HC908AS60A, MC68HC908AZ60A, and MC68HC908AZ60E are members of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
MC68HC908AZ60A, MC68HC908AS60A, MC68HC908AZ60E Data Sheet
2006
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(I5.1.417156) 2800 0 R (I5.1.417157) 2801 0 R (I5.1.417159) 2802 0 R (I5.1.417728) 2803 0 R (I5.1.418705) 2804 0 R
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(I5.1.423694) 2810 0 R (I5.1.423747) 2811 0 R (I5.1.423764) 2812 0 R (I5.1.423808) 2813 0 R (I5.1.424117) 2814 0 R
(I5.1.427755) 2815 0 R (I5.1.427756) 2816 0 R (I5.1.439483) 2817 0 R (I5.1.439700) 2818 0 R (I5.1.439702) 2819 0 R
(I6.1.399971) 2820 0 R (I6.1.399984) 2821 0 R (I6.1.399993) 2822 0 R (I6.1.400718) 2823 0 R (I6.1.451781) 2824 0 R
(I6.1.463450) 2825 0 R (I6.1.486063) 2826 0 R (I6.1.487636) 2827 0 R (I6.1.487638) 2828 0 R (I6.1.499514) 2829 0 R
(I6.1.499560) 2830 0 R (I6.1.499605) 2831 0 R (I6.1.500067) 2832 0 R (I6.1.508884) 2833 0 R (I7.1.390195) 2834 0 R
(I7.1.390196) 2835 0 R (I7.1.390199) 2836 0 R (I7.1.390202) 2837 0 R (I7.1.390212) 2838 0 R (I8.1.390359) 2839 0 R
(I8.1.390362) 2840 0 R (I8.1.390520) 2841 0 R (I8.1.390576) 2842 0 R (I8.1.392093) 2843 0 R]
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endobj
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/Limits [(I8.1.392105) (L34)]
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(I8.1.396686) 2849 0 R (I8.1.399234) 2850 0 R (I8.1.399920) 2851 0 R (I8.1.403725) 2852 0 R (I8.1.403726) 2853 0 R
(I8.1.403727) 2854 0 R (I8.1.404799) 2855 0 R (I8.1.405309) 2856 0 R (I8.1.405328) 2857 0 R (I8.1.405343) 2858 0 R
(I8.1.405386) 2859 0 R (I9.1.390359) 2860 0 R (I9.1.390362) 2861 0 R (I9.1.390520) 2862 0 R (I9.1.390576) 2863 0 R
(I9.1.392357) 2864 0 R (I9.1.392369) 2865 0 R (I9.1.396686) 2866 0 R (I9.1.399234) 2867 0 R (I9.1.403725) 2868 0 R
(I9.1.403726) 2869 0 R (I9.1.403727) 2870 0 R (I9.1.404799) 2871 0 R (I9.1.405438) 2872 0 R (I9.1.406321) 2873 0 R
(I9.1.406322) 2874 0 R (I9.1.406367) 2875 0 R (I9.1.406368) 2876 0 R (I9.1.406369) 2877 0 R (I9.1.406411) 2878 0 R
(I9.1.406412) 2879 0 R (L1) 2880 0 R (L10) 2881 0 R (L11) 2882 0 R (L12) 2883 0 R
(L13) 2884 0 R (L14) 2885 0 R (L15) 2886 0 R (L16) 2887 0 R (L17) 2888 0 R
(L18) 2889 0 R (L19) 2890 0 R (L2) 2891 0 R (L20) 2892 0 R (L21) 2893 0 R
(L22) 2894 0 R (L23) 2895 0 R (L24) 2896 0 R (L25) 2897 0 R (L26) 2898 0 R
(L27) 2899 0 R (L28) 2900 0 R (L29) 2901 0 R (L3) 2902 0 R (L30) 2903 0 R
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/Limits [(L35) (M11.9.41462.figuretitlewide.Figure.1.EEPROM1.Register.Summary)]
/Names [(L35) 2908 0 R (L36) 2909 0 R (L37) 2910 0 R (L4) 2911 0 R (L5) 2912 0 R
(L6) 2913 0 R (L7) 2914 0 R (L8) 2915 0 R (L9) 2916 0 R (M10.8.newlink.231) 2917 0 R
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(M10.9.13390.sectionxxx.538.EEPROM.NonVolatile.Register.EENVR.and.EEPROM.Array.Configuration) 2923 0 R (M10.9.13991.heading1.Introduction) 2924 0 R (M10.9.18406.heading1.EEPROM1.Register.Descriptions) 2925 0 R (M10.9.19005.figuretitle.Figure.53..EEPROM.Control.Register.EECR) 2926 0 R (M10.9.19751.heading2.EEPROM1.Timebase.Requirements) 2927 0 R
(M10.9.20009.sectionxx.64.Functional.Description) 2928 0 R (M10.9.21092.figuretitle.Figure.7..EEDIV1.Nonvolatile.Register.EEDIV1LNVR) 2929 0 R (M10.9.22983.tabletitle.Table.2.Example.Selective.Bit.Programming.Description) 2930 0 R (M10.9.24429.figuretitle.Figure.4..EEPROM2.Nonvolatile.Register.EENVR2) 2931 0 R (M10.9.24452.tabletitle.Table.1.EEPROM1.Array.Address.Blocks) 2932 0 R
(M10.9.24786.sectionxx.63.Features) 2933 0 R (M10.9.25293.heading2.EEPROM1.Control.Register) 2934 0 R (M10.9.26614.heading2.EEPROM1.Timebase.Divider.Register) 2935 0 R (M10.9.28394.heading1.EEPROM1.Register.Summary) 2936 0 R (M10.9.28754.sectionxxxx.6492.Stop.Mode) 2937 0 R
(M10.9.32813.figuretitle.Figure.5..EEDIV1.Nonvolatile.Register.EEDIV1HNVR) 2938 0 R (M10.9.34986.sectionxxxx.6491.Wait.Mode) 2939 0 R (M10.9.37938.heading2.EEPROM1.Configuration) 2940 0 R (M10.9.37993.heading3.EEPROM1.Erasing) 2941 0 R (M10.9.41462.figuretitlewide.Figure.1.EEPROM1.Register.Summary) 2942 0 R
(M10.9.61628.sectionx.Chapter.6.EEPROM1.Memory) 2943 0 R (M10.9.71524.heading1.LowPower.Modes) 2944 0 R (M10.9.72356.heading2.EEPROM1.Timebase.Divider.NonVolatile.Register) 2945 0 R (M10.9.80231.figuretitle.Figure.52..EEPROM.Control.Register.EECR) 2946 0 R (M10.9.96292.heading2.EEPROM1.Programming.and.Erasing) 2947 0 R
(M11.8.newlink.231) 2948 0 R (M11.9.10185.heading2.EEPROM1.Security.Option) 2949 0 R (M11.9.10837.heading2.EEPROM1.Block.Protection) 2950 0 R (M11.9.11659.figuretitle.Figure.6..EEDIV1.Divider.High.Register.EEDIV1H) 2951 0 R (M11.9.12982.heading3.EEPROM1.Programming) 2952 0 R
(M11.9.13226.heading2.EEPROM1.Array.Configuration.Register) 2953 0 R (M11.9.13390.sectionxxx.538.EEPROM.NonVolatile.Register.EENVR.and.EEPROM.Array.Configuration) 2954 0 R (M11.9.13991.heading1.Introduction) 2955 0 R (M11.9.19005.figuretitle.Figure.53..EEPROM.Control.Register.EECR) 2956 0 R (M11.9.19751.heading2.EEPROM1.Timebase.Requirements) 2957 0 R
(M11.9.20009.sectionxx.64.Functional.Description) 2958 0 R (M11.9.21092.figuretitle.Figure.7..EEDIV1.Nonvolatile.Register.EEDIV1LNVR) 2959 0 R (M11.9.22983.tabletitle.Table.2.Example.Selective.Bit.Programming.Description) 2960 0 R (M11.9.23519.sectionx.Chapter.7.EEPROM2.Memory) 2961 0 R (M11.9.24429.figuretitle.Figure.4..EEPROM2.Nonvolatile.Register.EENVR2) 2962 0 R
(M11.9.24452.tabletitle.Table.1.EEPROM1.Array.Address.Blocks) 2963 0 R (M11.9.24786.sectionxx.63.Features) 2964 0 R (M11.9.25293.heading2.EEPROM1.Control.Register) 2965 0 R (M11.9.28754.sectionxxxx.6492.Stop.Mode) 2966 0 R (M11.9.32813.figuretitle.Figure.5..EEDIV1.Nonvolatile.Register.EEDIV1HNVR) 2967 0 R
(M11.9.34986.sectionxxxx.6491.Wait.Mode) 2968 0 R (M11.9.37938.heading2.EEPROM1.Configuration) 2969 0 R (M11.9.37993.heading3.EEPROM1.Erasing) 2970 0 R (M11.9.41462.figuretitlewide.Figure.1.EEPROM1.Register.Summary) 2971 0 R]
>>
endobj
66 0 obj
<<
/Limits [(M11.9.44794.heading2.EEPROM2.Programming.and.Erasing) (M14.9.21391.sectionxx.103.Features)]
/Names [(M11.9.44794.heading2.EEPROM2.Programming.and.Erasing) 2972 0 R (M11.9.52524.heading2.EEPROM2.Timebase.Divider.NonVolatile.Register) 2973 0 R (M11.9.57755.heading1.EEPROM2.Register.Descriptions) 2974 0 R (M11.9.60911.heading2.EEPROM2.Timebase.Divider.Register) 2975 0 R (M11.9.68919.heading1.EEPROM2.Register.Summary) 2976 0 R
(M11.9.80231.figuretitle.Figure.52..EEPROM.Control.Register.EECR) 2977 0 R (M11.9.80425.heading1.LowPower.Modes) 2978 0 R (M12.9.70017.figuretitle.Figure.11..CPU.Registers) 2979 0 R (M12.9.86244.tabletitle.Table.61..Instruction.Set.Summary.Sheet.1.of.7) 2980 0 R (M12.9.97010.tabletitle.Table.62..Opcode.Map) 2981 0 R
(M13.9.10655.figuretitle.Figure.119.Interrupt.Entry) 2982 0 R (M13.9.11321.sectionx.Chapter.9.System.Integration.Module.SIM) 2983 0 R (M13.9.12579.sectionxx.97.LowPower.Modes) 2984 0 R (M13.9.12954.sectionxx.94.Reset.and.System.Initialization) 2985 0 R (M13.9.15274.sectionxxxx.9422.Computer.Operating.Properly.COP.Reset) 2986 0 R
(M13.9.15360.sectionxxx.953.SIM.Counter.and.Reset.States) 2987 0 R (M13.9.16145.tabletitle.Table.19..PIN.Bit.Set.Timing) 2988 0 R (M13.9.17023.sectionxxx.962.Reset) 2989 0 R (M13.9.18790.sectionxxx.963.Break.Interrupts) 2990 0 R (M13.9.21430.figuretitle.Figure.19..External.Reset.Timing) 2991 0 R
(M13.9.22192.figuretitle.Figure.71..SIM.Block.Diagram) 2992 0 R (M13.9.23185.figuretitle.Figure.118..Interrupt.Recognition.Example.3) 2993 0 R (M13.9.25667.sectionxxx.961.Interrupts) 2994 0 R (M13.9.26302.sectionxxx.951.SIM.Counter.During.PowerOn.Reset) 2995 0 R (M13.9.26711.sectionxxx.952.SIM.Counter.During.Stop.Mode.Recovery) 2996 0 R
(M13.9.27994.figuretitle.Figure.95..Internal.Reset.Timing) 2997 0 R (M13.9.29372.sectionxxx.941.External.Pin.Reset) 2998 0 R (M13.9.30036.sectionxxx.142.Active.Reset.from.an.Internal.Source) 2999 0 R (M13.9.30196.sectionxx.96.Program.Exception.Control) 3000 0 R (M13.9.31834.sectionxxx.964.Status.Flag.Protection.in.Break.Mode) 3001 0 R
(M13.9.31884.sectionxxxx.9425.LowVoltage.Inhibit.LVI.Reset) 3002 0 R (M13.9.31991.sectionxxxx.9423.Illegal.Opcode.Reset) 3003 0 R (M13.9.34181.sectionxxxx.9421.PowerOn.Reset) 3004 0 R (M13.9.34779.figuretitle.Figure.113.Sources.of.Internal.Reset) 3005 0 R (M13.9.36773.sectionxxxx.9424.Illegal.Address.Reset) 3006 0 R
(M13.9.37424.figuretitle.Figure.79..Interrupt.Recovery) 3007 0 R (M13.9.37476.sectionxx.93.SIM.Bus.Clock.Control.and.Generation) 3008 0 R (M13.9.40893.sectionxx.92.Introduction) 3009 0 R (M13.9.41282.sectionxxx.971.Wait.Mode) 3010 0 R (M13.9.41514.sectionxxx.931.Bus.Timing) 3011 0 R
(M13.9.42118.sectionxxx.933.Clocks.in.Stop.Mode.and.Wait.Mode) 3012 0 R (M13.9.42434.sectionxxx.932.Clock.Startup.from.POR.or.LVI.Reset) 3013 0 R (M13.9.48742.sectionxxx.793.SIM.Break.Flag.Control.Register.SBFCR) 3014 0 R (M13.9.53481.sectionxxx.482.SIM.Reset.Status.Register.SRSR) 3015 0 R (M13.9.55852.tabletitle.Table.11.Clock.Signal.Name.Conventions) 3016 0 R
(M13.9.56260.figuretitle.Figure.714..Stop.Mode.Entry.Timing) 3017 0 R (M13.9.60264.sectionxx.76.SIM.Counter) 3018 0 R (M13.9.65741.sectionxxx.481.SIM.Break.Status.Register.SBRSTest.Control.Register.TECR) 3019 0 R (M13.9.66383.figuretitle.Figure.16.POR.Recovery) 3020 0 R (M13.9.67824.sectionxxx.152.Stop.Mode) 3021 0 R
(M13.9.74993.tabletitle.Table.71..SIM.IO.Register.Summary) 3022 0 R (M13.9.85338.sectionxx.15.SIM.Control.Registers) 3023 0 R (M13.9.89157.figuretitle.Figure.426..Wait.Mode.Entry.Timing) 3024 0 R (M13.9.91967.figuretitle.Figure.130.Wait.Recovery.from.Interrupt.or.Break) 3025 0 R (M13.9.92875.figuretitle.Figure.132.Wait.Recovery.From.Reset) 3026 0 R
(M13.9.93627.figuretitle.Figure.117.Interrupt.Processing) 3027 0 R (M13.9.99849.figuretitle.Figure.12.CGM.Clock.Signals) 3028 0 R (M14.9.10836.sectionxxx.1052.Crystal.Amplifier.Output.Pin.OSC2) 3029 0 R (M14.9.11035.sectionxxx.122.Phase.Locked.Loop.Submodule.PLL) 3030 0 R (M14.9.11251.heading2.CGM.External.Connections) 3031 0 R
(M14.9.11740.sectionxxx.1058.CGM.CPU.Interrupt.CGMINT) 3032 0 R (M14.9.13554.sectionxx.109.CGM.During.Break.Interrupts) 3033 0 R (M14.9.14259.sectionxxx.1081.Wait.Mode) 3034 0 R (M14.9.21391.sectionxx.103.Features) 3035 0 R]
>>
endobj
67 0 obj
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(M14.9.26667.sectionxx.12.Functional.Description) 3041 0 R (M14.9.28163.sectionxxx.143.PLL.Programming.Register.PPG) 3042 0 R (M14.9.28807.sectionxxx.1054.Analog.Power.Pin.VDDA) 3043 0 R (M14.9.29000.sectionxxx.1056.Crystal.Output.Frequency.Signal.CGMXCLK) 3044 0 R (M14.9.30721.sectionxxx.123.Acquisition.and.Tracking.Modes) 3045 0 R
(M14.9.31430.sectionxx.108.LowPower.Modes) 3046 0 R (M14.9.34227.heading3.Programming.the.PLL) 3047 0 R (M14.9.34745.sectionxx.105.IO.Signals) 3048 0 R (M14.9.36466.figuretitle.Figure.12..CGM.External.Connections) 3049 0 R (M14.9.37537.sectionxx.106.CGM.Registers) 3050 0 R
(M14.9.37889.bitname.Circuits) 3051 0 R (M14.9.38875.figuretitle.Figure.102..IO.Register.Summary) 3052 0 R (M14.9.40722.sectionxxx.1051.Crystal.Amplifier.Input.Pin.OSC1) 3053 0 R (M14.9.41596.sectionxx.102.Introduction) 3054 0 R (M14.9.41893.sectionxxx.123.Manual.and.Automatic.Bandwidth.Modes) 3055 0 R
(M14.9.50264.tabletitle.Table.102..Variable.Definitions) 3056 0 R (M14.9.51720.sectionxxx.144.Timer.Control.Register4..Interrupt.EnablePrescaler.Select.TCTL4) 3057 0 R (M14.9.54951.sectionxxxx.1832.Parametric.Influences.on.tACQ.tLCK) 3058 0 R (M14.9.55130.sectionxxxx.1833.Choosing.a.Filter.Capacitor) 3059 0 R (M14.9.55804.sectionxx.16.Interrupts) 3060 0 R
(M14.9.59659.sectionxxx.142.PLL.Bandwidth.Control.Register.PBWC) 3061 0 R (M14.9.63843.sectionxxx.184.Acquisition.Time) 3062 0 R (M14.9.66934.sectionxxxx.1831.AcquisitionLock.Time.Definitions) 3063 0 R (M14.9.72160.sectionx.Chapter.10.Clock.Generator.Module.CGM) 3064 0 R (M14.9.72373.sectionxxx.123.Base.Clock.Selector.Circuit) 3065 0 R
(M14.9.78487.figure1.Figure.11.CGMA.Block.Diagram) 3066 0 R (M14.9.79952.sectionxxx.843.External.Filter.Capacitor.Pin.CGMXFC) 3067 0 R (M14.9.92707.sectionxxxx.1834.Reaction.Time.Calculation) 3068 0 R (M15.9.14711.sectionxx.53.Functional.Description) 3069 0 R (M15.9.34513.sectionxx.112.Introduction) 3070 0 R
(M15.9.89253.sectionx.Chapter.11.Configuration.Register.CONFIG1) 3071 0 R (M16.9.14711.sectionxx.53.Functional.Description) 3072 0 R (M16.9.30292.sectionxx.122.Introduction) 3073 0 R (M17.9.10706.sectionxxx.1343.TIM.During.Break.Interrupts) 3074 0 R (M17.9.10796.sectionxx.136.Break.Module.Registers) 3075 0 R
(M17.9.14410.sectionxx.135.LowPower.Modes) 3076 0 R (M17.9.16123.sectionxxx.1341.Flag.Protection.During.Break.Interrupts) 3077 0 R (M17.9.17611.sectionxxx.1361.Break.Status.and.Control.Register) 3078 0 R (M17.9.18957.sectionxxx.1342.CPU.During.Break.Interrupts) 3079 0 R (M17.9.24053.sectionxxx.1351.Wait.Mode) 3080 0 R
(M17.9.26635.figuretitle.Figure.131..Break.Module.Block.Diagram) 3081 0 R (M17.9.31248.sectionxx.132.Introduction) 3082 0 R (M17.9.32071.sectionxxx.1362.Break.Address.Registers) 3083 0 R (M17.9.34879.sectionxx.133.Features) 3084 0 R (M17.9.35009.sectionxx.134.Functional.Description) 3085 0 R
(M17.9.39887.sectionxxx.1344.COP.During.Break.Interrupts) 3086 0 R (M17.9.40205.sectionxxx.1352.Stop.Mode) 3087 0 R (M17.9.44503.sectionx.Chapter.13.Break.Module.BRK) 3088 0 R (M18.9.14757.sectionxxx.1445.Commands) 3089 0 R (M18.9.15674.sectionxxx.1446.Baud.Rate) 3090 0 R
(M18.9.17000.sectionxxx.1447.Security) 3091 0 R (M18.9.18599.sectionxxx.1441.Entering.Monitor.Mode) 3092 0 R (M18.9.22360.sectionxxx.247.MC68HC908AZ60A.Baud.Rate) 3093 0 R (M18.9.23125.sectionxx.144.Functional.Description) 3094 0 R (M18.9.27362.tabletitle.Table.43..Mode.Selection) 3095 0 R
(M18.9.30194.figuretitle.Figure.13..Sample.Monitor.Waveforms) 3096 0 R (M18.9.30863.sectionxx.142.Introduction) 3097 0 R (M18.9.32068.sectionxx.143.Features) 3098 0 R (M18.9.36642.sectionxxx.1444.Break.Signal) 3099 0 R]
>>
endobj
68 0 obj
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/Limits [(M18.9.36979.tabletitle.Table.87..RUN.Run.User.Program.Command) (M22.8.newlink.1223)]
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(M18.9.66695.tabletitle.Table.82..READ.Read.Memory.Command) 3105 0 R (M18.9.69605.tabletitle.Table.13..Mode.Differences) 3106 0 R (M18.9.79354.figuretitle.Figure.11..Monitor.Mode.Circuit) 3107 0 R (M18.9.80259.figuretitle.Figure.14..Read.Transaction) 3108 0 R (M18.9.88592.tabletitle.Table.9..Monitor.Baud.Rate.Selection) 3109 0 R
(M18.9.93821.figuretitle.Figure.12..Monitor.Data.Format) 3110 0 R (M19.9.10954.sectionxxx.1543.COPCTL.Write) 3111 0 R (M19.9.13356.sectionxx.153.Functional.Description) 3112 0 R (M19.9.21951.sectionxx.156.Interrupts) 3113 0 R (M19.9.24091.sectionxxx.1541.CGMXCLK) 3114 0 R
(M19.9.24318.sectionxxx.1548.COPL) 3115 0 R (M19.9.25524.figuretitle.Figure.151..COP.Block.Diagram) 3116 0 R (M19.9.27043.sectionxx.152.Introduction) 3117 0 R (M19.9.27177.sectionxxx.1547.COPD) 3118 0 R (M19.9.27737.sectionxxx.1542.STOP.Instruction) 3119 0 R
(M19.9.27957.sectionxx.154.IO.Signals) 3120 0 R (M19.9.29193.sectionxx.158.LowPower.Modes) 3121 0 R (M19.9.29410.sectionxxx.1544.PowerOn.Reset) 3122 0 R (M19.9.35383.sectionx.Chapter.15.Computer.Operating.Properly.COP) 3123 0 R (M19.9.37123.sectionxxx.1546.Reset.Vector.Fetch) 3124 0 R
(M19.9.37211.sectionxx.139.COP.Module.During.Break.Interrupts) 3125 0 R (M19.9.38165.sectionxxx.1545.Internal.Reset) 3126 0 R (M19.9.38221.sectionxxx.1581.Wait.Mode) 3127 0 R (M19.9.40067.sectionxx.157.Monitor.Mode) 3128 0 R (M19.9.41328.sectionxxx.1582.Stop.Mode) 3129 0 R
(M19.9.78911.sectionxx.134.COP.Control.Register.COPCTL) 3130 0 R (M20.9.14457.sectionxxx.1643.False.Reset.Protection) 3131 0 R (M20.9.15354.sectionxxx.1641.Polled.LVI.Operation) 3132 0 R (M20.9.15908.sectionxx.162.Introduction) 3133 0 R (M20.9.18746.sectionxx.168.Stop.Mode) 3134 0 R
(M20.9.19160.heading2.Wait.Mode) 3135 0 R (M20.9.26753.sectionxx.166.LVI.Interrupts) 3136 0 R (M20.9.32715.sectionxxx.1442.Forced.Reset.Operation) 3137 0 R (M20.9.34307.sectionxx.164.Functional.Description) 3138 0 R (M20.9.35479.sectionxx.163.Features) 3139 0 R
(M20.9.36880.sectionxx.165.LVI.Status.Register) 3140 0 R (M20.9.41003.sectionxx.167.Wait.Mode) 3141 0 R (M20.9.73433.figuretitle.Figure.161..LVI.Module.Block.Diagram) 3142 0 R (M20.9.80559.sectionx.Chapter.16.LowVoltage.Inhibit.LVI) 3143 0 R (M20.9.92717.tabletitle.Table.182..LVIOUT.Bit.Indication) 3144 0 R
(M21.9.16570.figuretitle.Figure.81.IRQ.Module.Block.Diagram) 3145 0 R (M21.9.19376.sectionxx.176.IRQ.Module.During.Break.Interrupts) 3146 0 R (M21.9.23080.sectionxx.175.IRQ.Pin) 3147 0 R (M21.9.24570.sectionxx.173.Features) 3148 0 R (M21.9.26255.sectionxx.172.Introduction) 3149 0 R
(M21.9.34966.sectionxx.174.Functional.Description) 3150 0 R (M21.9.36874.figuretitleindented.Figure.12..Interrupt.Flowchart) 3151 0 R (M21.9.62605.sectionxxx.1751.IRQ.Status.and.Control.Register.ISCR) 3152 0 R (M21.9.81093.sectionx.Chapter.17.External.Interrupt.Module.IRQ) 3153 0 R (M22.8.newlink.121) 3154 0 R
(M22.8.newlink.122) 3155 0 R (M22.8.newlink.1221) 3156 0 R (M22.8.newlink.1222) 3157 0 R (M22.8.newlink.12221) 3158 0 R (M22.8.newlink.12222) 3159 0 R
(M22.8.newlink.12223) 3160 0 R (M22.8.newlink.12224) 3161 0 R (M22.8.newlink.12225) 3162 0 R (M22.8.newlink.1223) 3163 0 R]
>>
endobj
69 0 obj
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/Limits [(M22.8.newlink.12231) (M22.9.37001.figuretitle.Figure.2..Fast.Data)]
/Names [(M22.8.newlink.12231) 3164 0 R (M22.8.newlink.12232) 3165 0 R (M22.8.newlink.12233) 3166 0 R (M22.8.newlink.12234) 3167 0 R (M22.8.newlink.12235) 3168 0 R
(M22.8.newlink.12236) 3169 0 R (M22.8.newlink.123) 3170 0 R (M22.8.newlink.1231) 3171 0 R (M22.8.newlink.1232) 3172 0 R (M22.8.newlink.124) 3173 0 R
(M22.8.newlink.1241) 3174 0 R (M22.8.newlink.1242) 3175 0 R (M22.8.newlink.125) 3176 0 R (M22.8.newlink.1251) 3177 0 R (M22.8.newlink.1252) 3178 0 R
(M22.8.newlink.1253) 3179 0 R (M22.8.newlink.1254) 3180 0 R (M22.8.newlink.1255) 3181 0 R (M22.8.newlink.1256) 3182 0 R (M22.8.newlink.1257) 3183 0 R
(M22.8.newlink.f121) 3184 0 R (M22.8.newlink.f122) 3185 0 R (M22.8.newlink.f123) 3186 0 R (M22.8.newlink.f124) 3187 0 R (M22.8.newlink.f125) 3188 0 R
(M22.8.newlink.t121) 3189 0 R (M22.8.newlink.t122) 3190 0 R (M22.8.newlink.t123) 3191 0 R (M22.9.10855.tabletitle.Table.112..Character.Format.Selection) 3192 0 R (M22.9.10935.sectionxxxx.18521.Character.Length) 3193 0 R
(M22.9.11635.figuretitle.Figure.111..SCI.Module.Block.Diagram) 3194 0 R (M22.9.12725.sectionxxxx.18532.Character.Reception) 3195 0 R (M22.9.14480.sectionxxx.1852.Transmitter) 3196 0 R (M22.9.15798.tabletitle.Table.113..Baud.Rate.Prescaling) 3197 0 R (M22.9.15948.tabletitle.Table.145..Data.Bit.Recovery) 3198 0 R
(M22.9.16490.sectionx.Chapter.18.Serial.Communications.Interface.SCI) 3199 0 R (M22.9.18239.sectionxx.186.LowPower.Modes) 3200 0 R (M22.9.18364.figuretitle.Figure.114..SCI.Receiver.Block.Diagram) 3201 0 R (M22.9.18448.sectionxxxx.18533.Data.Sampling) 3202 0 R (M22.9.19199.sectionxxxx.18534.Framing.Errors) 3203 0 R
(M22.9.20037.sectionxxx.1881.PTE0SCTxD.Transmit.Data) 3204 0 R (M22.9.20082.sectionxxxx.18536.Receiver.Wakeup) 3205 0 R (M22.9.20219.sectionxxx.1882.PTE1SCRxD.Receive.Data) 3206 0 R (M22.9.20921.sectionxx.182.Introduction) 3207 0 R (M22.9.20921.sectionxxxx.18538.Error.Interrupts) 3208 0 R
(M22.9.21171.sectionxxx.1893.SCI.Control.Register.3) 3209 0 R (M22.9.22210.sectionxxx.1896.SCI.Data.Register) 3210 0 R (M22.9.22941.sectionxxxx.18535.Baud.Rate.Tolerance) 3211 0 R (M22.9.24413.sectionxx.184.Pin.Name.Conventions) 3212 0 R (M22.9.25768.sectionxxxx.18531.Character.Length) 3213 0 R
(M22.9.26261.sectionxx.189.IO.Registers) 3214 0 R (M22.9.27357.sectionxxx.1861.Wait.Mode) 3215 0 R (M22.9.28406.sectionxxx.1895.SCI.Status.Register.2) 3216 0 R (M22.9.28960.sectionxx.185.Functional.Description) 3217 0 R (M22.9.29019.sectionxxxx.18526.Transmitter.Interrupts) 3218 0 R
(M22.9.29667.sectionxxxx.18524.Idle.Characters) 3219 0 R (M22.9.31272.figuretitle.Figure.189..Slow.Data) 3220 0 R (M22.9.32869.sectionxx.187.SCI.During.Break.Module.Interrupts) 3221 0 R (M22.9.33407.sectionxxx.1851.Data.Format) 3222 0 R (M22.9.33836.sectionxx.183.Features) 3223 0 R
(M22.9.34686.sectionxxx.1862.Stop.Mode) 3224 0 R (M22.9.35120.figuretitle.Figure.115..Receiver.Data.Sampling) 3225 0 R (M22.9.35225.sectionxxxx.18523.Break.Characters) 3226 0 R (M22.9.37001.figuretitle.Figure.2..Fast.Data) 3227 0 R]
>>
endobj
70 0 obj
<<
/Limits [(M22.9.37791.sectionxx.188.IO.Signals) (M23.9.31104.sectionxxx.1964.Transmission.Initiation.Latency)]
/Names [(M22.9.37791.sectionxx.188.IO.Signals) 3228 0 R (M22.9.39423.tabletitle.Table.117..Baud.Rate.Selection.Examples) 3229 0 R (M22.9.39817.sectionxxx.1853.Receiver) 3230 0 R (M22.9.40059.sectionxxx.1892.SCI.Control.Register.2) 3231 0 R (M22.9.40194.sectionxxx.1897.SCI.Baud.Rate.Register) 3232 0 R
(M22.9.40579.sectionxxxx.18525.Inversion.of.Transmitted.Output) 3233 0 R (M22.9.41570.sectionxxxx.18522.Character.Transmission) 3234 0 R (M22.9.41762.sectionxxxx.18537.Receiver.Interrupts) 3235 0 R (M22.9.43553.figuretitle.Figure.1410..Flag.Clearing.Sequence) 3236 0 R (M22.9.44656.figuretitle.Figure.113..SCI.Transmitter) 3237 0 R
(M22.9.47925.tabletitle.Table.146..Stop.Bit.Verification) 3238 0 R (M22.9.61464.sectionxxx.1461.SCI.Control.Register.1.SCC1) 3239 0 R (M22.9.67672.tabletitle.Table.114..Baud.Rate.Selection) 3240 0 R (M22.9.77257.tabletitle.Table.131..Pin.Name.Conventions) 3241 0 R (M22.9.82020.sectionxxx.1164.SCI.Status.Register.1.SCS1) 3242 0 R
(M22.9.90988.tabletitle.Table.5..Start.Bit.Verification) 3243 0 R (M22.9.95033.figuretitle.Figure.112..SCI.Data.Formats) 3244 0 R (M23.8.newlink.111) 3245 0 R (M23.8.newlink.112) 3246 0 R (M23.8.newlink.1121) 3247 0 R
(M23.8.newlink.1122) 3248 0 R (M23.8.newlink.1123) 3249 0 R (M23.8.newlink.1124) 3250 0 R (M23.8.newlink.113) 3251 0 R (M23.8.newlink.114) 3252 0 R
(M23.8.newlink.1141) 3253 0 R (M23.8.newlink.1142) 3254 0 R (M23.8.newlink.115) 3255 0 R (M23.8.newlink.1151) 3256 0 R (M23.8.newlink.1152) 3257 0 R
(M23.8.newlink.1153) 3258 0 R (M23.8.newlink.1154) 3259 0 R (M23.8.newlink.1155) 3260 0 R (M23.8.newlink.116) 3261 0 R (M23.8.newlink.1161) 3262 0 R
(M23.8.newlink.1162) 3263 0 R (M23.8.newlink.1163) 3264 0 R (M23.8.newlink.f111) 3265 0 R (M23.8.newlink.f112) 3266 0 R (M23.8.newlink.f113) 3267 0 R
(M23.8.newlink.t111) 3268 0 R (M23.9.10017.sectionxxx.19111.Wait.Mode) 3269 0 R (M23.9.11376.figuretitle.Figure.12..FullDuplex.MasterSlave.Connections) 3270 0 R (M23.9.13051.sectionxxx.19135.VSS.Clock.Ground) 3271 0 R (M23.9.13068.sectionxx.134.SPI.Transfer.Formats) 3272 0 R
(M23.9.13446.sectionxxx.1963.Transmission.Format.When.CPHA1) 3273 0 R (M23.9.16007.sectionxxx.1971.Overflow.Error) 3274 0 R (M23.9.16107.sectionxx.1914.IO.Registers) 3275 0 R (M23.9.17361.sectionxx.192.Introduction) 3276 0 R (M23.9.17499.figuretitle.Figure.131..SPI.IO.Register.Summary) 3277 0 R
(M23.9.18197.sectionxxx.19143.SPI.Data.Register) 3278 0 R (M23.9.18901.sectionxxx.19133.SPSCK.Serial.Clock) 3279 0 R (M23.9.21988.sectionxxx.1962.Transmission.Format.When.CPHA..0) 3280 0 R (M23.9.23606.sectionxxx.1952.Slave.Mode) 3281 0 R (M23.9.23781.sectionxx.197.Error.Conditions) 3282 0 R
(M23.9.24810.sectionxx.195.Functional.Description) 3283 0 R (M23.9.25593.figuretitle.Figure.135..Preferred.Method.of.Clearing.SPRF.When.OVRF.Interrupt.Is.Not) 3284 0 R (M23.9.26237.sectionxxx.19131.MISO.Master.InSlave.Out) 3285 0 R (M23.9.26959.sectionxx.1911.LowPower.Modes) 3286 0 R (M23.9.28406.sectionxxx.1961.Clock.Phase.and.Polarity.Controls) 3287 0 R
(M23.9.29213.sectionxxx.172.SPI.Status.and.Control.Register.SPSCR) 3288 0 R (M23.9.29321.sectionxx.1912.SPI.During.Break.Interrupts) 3289 0 R (M23.9.30238.tabletitle.Table.14..SPI.Interrupts) 3290 0 R (M23.9.31104.sectionxxx.1964.Transmission.Initiation.Latency) 3291 0 R]
>>
endobj
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/Limits [(M23.9.31523.sectionxx.137.Interrupts) (M25.9.24335.sectionxx.218.IO.Registers)]
/Names [(M23.9.31523.sectionxx.137.Interrupts) 3292 0 R (M23.9.32612.sectionxx.1913.IO.Signals) 3293 0 R (M23.9.35380.sectionxxx.19112.Stop.Mode) 3294 0 R (M23.9.35555.sectionxx.193.Features) 3295 0 R (M23.9.36257.sectionxx.199.Queuing.Transmission.Data) 3296 0 R
(M23.9.38947.sectionxx.194.Pin.Name.and.Register.Name.Conventions) 3297 0 R (M23.9.39156.sectionxxx.19132.MOSI.Master.OutSlave.In) 3298 0 R (M23.9.41733.sectionxxx.1951.Master.Mode) 3299 0 R (M23.9.45838.tabletitle.Table.162..IO.Register.Addresses) 3300 0 R (M23.9.48169.figuretitle.Figure.134..Missed.Read.of.Overrun.Condition) 3301 0 R
(M23.9.51052.figuretitle.Figure.11..SPI.Module.Block.Diagram) 3302 0 R (M23.9.56242.tabletitle.Table.11..Baud.Rate.Selection) 3303 0 R (M23.9.61921.sectionxxx.13124.SS.Slave.Select) 3304 0 R (M23.9.62969.sectionxxx.171.SPI.Control.Register.SPCR) 3305 0 R (M23.9.64548.figuretitle.Figure.135..Delay.from.Write.SPDR.to.Transfer.Start.Master) 3306 0 R
(M23.9.65242.figuretitle.Figure.13..SPI.DataClock.Timing.Diagram) 3307 0 R (M23.9.67932.figuretitle.Figure.134..CPHA.Equals.One.SPI.Transfer.Format) 3308 0 R (M23.9.70780.sectionxxx.1351.Mode.Fault.Error.MODF) 3309 0 R (M23.9.78773.tabletitle.Table.132..SPI.Configuration) 3310 0 R (M23.9.80754.figuretitle.Figure.15..CPHASS.Timing) 3311 0 R
(M23.9.83732.sectionx.Chapter.19.Serial.Peripheral.Interface.SPI) 3312 0 R (M23.9.89868.sectionxx.139.Resetting.the.SPI) 3313 0 R (M23.9.93586.tabletitle.Table.161..IO.Register.Addresses) 3314 0 R (M23.9.96749.figuretitle.Figure.137..SPRFSPTE.Interrupt.Timing) 3315 0 R (M23.9.98809.figuretitle.Figure.135..SPI.Interrupt.Generation) 3316 0 R
(M24.9.12126.sectionxx.203.Features) 3317 0 R (M24.9.13171.sectionxxx.2081.TIMB.Clock.Pin.PTD4ATD12TBCLK) 3318 0 R (M24.9.14347.sectionxxx.2082.TIMB.Channel.IO.Pins.PTF5TBCH1PTF4TBCH0) 3319 0 R (M24.9.15912.sectionxxxx.20431.Unbuffered.Output.Compare) 3320 0 R (M24.9.16455.sectionxxxx.20442.Buffered.PWM.Signal.Generation) 3321 0 R
(M24.9.17878.sectionxx.202.Introduction) 3322 0 R (M24.9.18283.sectionxxx.2092.TIMB.Counter.Registers) 3323 0 R (M24.9.18831.sectionxxxx.20432.Buffered.Output.Compare) 3324 0 R (M24.9.23266.sectionxxx.2042.Input.Capture) 3325 0 R (M24.9.24304.tabletitle.Table.12..Mode.Edge.and.Level.Selection) 3326 0 R
(M24.9.24679.sectionxxxx.20441.Unbuffered.PWM.Signal.Generation) 3327 0 R (M24.9.25969.sectionxx.208.IO.Signals) 3328 0 R (M24.9.27336.sectionxxx.2041.TIMB.Counter.Prescaler) 3329 0 R (M24.9.28110.sectionxx.206.LowPower.Modes) 3330 0 R (M24.9.28643.sectionxx.205.Interrupts) 3331 0 R
(M24.9.28867.tabletitle.Table.11..Prescaler.Selection) 3332 0 R (M24.9.29470.sectionxx.207.TIMB.During.Break.Interrupts) 3333 0 R (M24.9.30151.sectionxxx.1233.Output.Compare) 3334 0 R (M24.9.34361.sectionxx.209.IO.Registers) 3335 0 R (M24.9.35513.sectionxxx.2093.TIMB.Counter.Modulo.Registers) 3336 0 R
(M24.9.37578.sectionxxx.1281.Timer.Status.and.Control.Register.TSC) 3337 0 R (M24.9.37739.sectionxxxx.20443.PWM.Initialization) 3338 0 R (M24.9.38653.sectionxxx.2061.Wait.Mode) 3339 0 R (M24.9.39927.sectionxx.204.Functional.Description) 3340 0 R (M24.9.42415.sectionxxx.1795.TIM.Channel.Registers) 3341 0 R
(M24.9.60403.figuretitle.Figure.11..TIM.Block.Diagram) 3342 0 R (M24.9.65500.figuretitleindented.Figure.12..PWM.Period.and.Pulse.Width) 3343 0 R (M24.9.68893.figuretitle.Figure.18..CHxMAX.Latency) 3344 0 R (M24.9.69348.sectionxxx.134.Pulse.Width.Modulation.PWM) 3345 0 R (M24.9.73299.sectionxxx.185.Timer.Channel.Status.and.Control.Registers.TSC0TSC3) 3346 0 R
(M24.9.78236.sectionxxx.1762.Stop.Mode) 3347 0 R (M24.9.84548.sectionx.Chapter.20.Timer.Interface.Module.B.TIMB) 3348 0 R (M25.9.11299.sectionxxx.2161.Wait.Mode) 3349 0 R (M25.9.13073.sectionxx.213.Features) 3350 0 R (M25.9.16332.sectionxxx.2183.TIM.Counter.Modulo.Registers) 3351 0 R
(M25.9.17735.sectionxx.215.TIM.Counter.Prescaler) 3352 0 R (M25.9.21128.sectionxxx.2162.Stop.Mode) 3353 0 R (M25.9.23845.sectionxx.217.TIM.During.Break.Interrupts) 3354 0 R (M25.9.24335.sectionxx.218.IO.Registers) 3355 0 R]
>>
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/Limits [(M25.9.28867.tabletitle.Table.11..Prescaler.Selection) (M26.9.36050.tabletitle.Table.127..Port.F.Pin.Functions)]
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(M25.9.38289.sectionxx.212.Introduction) 3361 0 R (M25.9.42199.sectionxxx.2182.TIM.Counter.Registers) 3362 0 R (M26.8.newlink.141) 3363 0 R (M26.8.newlink.1412) 3364 0 R (M26.8.newlink.142) 3365 0 R
(M26.8.newlink.1421) 3366 0 R (M26.8.newlink.1422) 3367 0 R (M26.8.newlink.143) 3368 0 R (M26.8.newlink.1431) 3369 0 R (M26.8.newlink.1432) 3370 0 R
(M26.8.newlink.144) 3371 0 R (M26.8.newlink.1441) 3372 0 R (M26.8.newlink.1442) 3373 0 R (M26.8.newlink.145) 3374 0 R (M26.8.newlink.1451) 3375 0 R
(M26.8.newlink.1452) 3376 0 R (M26.8.newlink.146) 3377 0 R (M26.8.newlink.1461) 3378 0 R (M26.8.newlink.1462) 3379 0 R (M26.8.newlink.f1412) 3380 0 R
(M26.8.newlink.f1415) 3381 0 R (M26.8.newlink.f1418) 3382 0 R (M26.8.newlink.f143) 3383 0 R (M26.8.newlink.f144) 3384 0 R (M26.8.newlink.f146) 3385 0 R
(M26.8.newlink.f149) 3386 0 R (M26.8.newlink.t141) 3387 0 R (M26.8.newlink.t142) 3388 0 R (M26.8.newlink.t143) 3389 0 R (M26.8.newlink.t145) 3390 0 R
(M26.8.newlink.t146) 3391 0 R (M26.9.11639.tabletitle.Table.125..Port.D.Pin.Functions) 3392 0 R (M26.9.11767.sectionxxx.22101.Port.H.Data.Register) 3393 0 R (M26.9.13576.sectionxxx.22102.Data.Direction.Register.H) 3394 0 R (M26.9.13593.sectionxxx.2282.Data.Direction.Register.F) 3395 0 R
(M26.9.13874.sectionxxx.2261.Port.D.Data.Register) 3396 0 R (M26.9.16319.sectionxx.227.Port.E) 3397 0 R (M26.9.17763.sectionxxx.2271.Port.E.Data.Register) 3398 0 R (M26.9.17869.tabletitle.Table.222.Port.B.Pin.Functions) 3399 0 R (M26.9.22193.sectionxx.223.Port.A) 3400 0 R
(M26.9.23234.sectionxxx.2292.Data.Direction.Register.G) 3401 0 R (M26.9.23746.sectionxxx.2251.Port.C.Data.Register) 3402 0 R (M26.9.24317.tabletitle.Table.221.Port.A.Pin.Functions) 3403 0 R (M26.9.26526.sectionxx.225.Port.C) 3404 0 R (M26.9.26529.figuretitle.Figure.1212..Port.D.IO.Circuit) 3405 0 R
(M26.9.26714.sectionxx.2210.Port.H) 3406 0 R (M26.9.28380.figuretitle.Figure.2219..Port.F.IO.Circuit) 3407 0 R (M26.9.29550.sectionxx.228.Port.F) 3408 0 R (M26.9.30511.sectionxxx.2281.Port.F.Data.Register) 3409 0 R (M26.9.30847.sectionxxx.2242.Data.Direction.Register.B) 3410 0 R
(M26.9.31532.sectionx.Chapter.22.InputOutput.Ports) 3411 0 R (M26.9.32149.sectionxxx.2272.Data.Direction.Register.E) 3412 0 R (M26.9.32326.sectionxxx.2231.Port.A.Data.Register) 3413 0 R (M26.9.32805.sectionxxx.2262.Data.Direction.Register.D) 3414 0 R (M26.9.33068.figuretitle.Figure.2216..Port.E.IO.Circuit) 3415 0 R
(M26.9.33860.figuretitle.Figure.2222..Port.G.IO.Circuit) 3416 0 R (M26.9.33951.sectionxxx.2291.Port.G.Data.Register) 3417 0 R (M26.9.35702.sectionxx.222.Introduction) 3418 0 R (M26.9.36050.tabletitle.Table.127..Port.F.Pin.Functions) 3419 0 R]
>>
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/Limits [(M26.9.36961.sectionxx.229.Port.G) (M27.9.35727.section.xxx.561.Message.Buffer.Outline)]
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(M26.9.41240.sectionxxx.2241.Port.B.Data.Register) 3425 0 R (M26.9.41891.sectionxx.226.Port.D) 3426 0 R (M26.9.50860.tabletitle.Table.126..Port.E.Pin.Functions) 3427 0 R (M26.9.61544.tabletitle.Table.124..Port.C.Pin.Functions) 3428 0 R (M26.9.63485.figuretitle.Figure.1924..Port.H.IO.Circuit) 3429 0 R
(M26.9.73655.tabletitle.Table.198..Port.F.Pin.Functions) 3430 0 R (M26.9.78095.tabletitle.Table.199..Port.G.Pin.Functions) 3431 0 R (M26.9.82665.figuretitle.Figure.126..Port.B.IO.Circuit) 3432 0 R (M26.9.PORT.A.IO.CIRCUIT) 3433 0 R (M27.9.10846.sectionxxx.2351.Background) 3434 0 R
(M27.9.10885.sectionx.Chapter.23.MSCAN.Controller.MSCAN08) 3435 0 R (M27.9.11140.sectionxxx.231411.MSCAN08.Transmit.Error.Counter) 3436 0 R (M27.9.12300.CaptionTbl.Table.16.Data.Length.Codes) 3437 0 R (M27.9.12643.HeadingL3.534.MCAN.interrupt.register.CINT) 3438 0 R (M27.9.13002.figuretitle.Figure26.Clocking.Scheme) 3439 0 R
(M27.9.13518.sectionxxx.23142.MSCAN08.Module.Control.Register) 3440 0 R (M27.9.14123.section.xxx.5125.MSCAN08.Bus.Timing.Register.1.CBTR1) 3441 0 R (M27.9.14612.section.xxx.5127.MSCAN08.Receiver.Interrupt.Enable.Register.CRIER) 3442 0 R (M27.9.14843.tabletitle.Table.239..Time.Segment.Values) 3443 0 R (M27.9.15352.section.xxx.5128.MSCAN08.Transmitter.Flag.Register.CTFLG) 3444 0 R
(M27.9.15690.figuretitle.Figure.235..Quadruple.8Bit.Maskable.Acceptance.Filters) 3445 0 R (M27.9.17054.figuretitle.Figure54.Sleep.Request..Acknowledge.Cycle) 3446 0 R (M27.9.17298.section.xx.54.Identifier.Filter) 3447 0 R (M27.9.17910.section.xxx.5124.MSCAN08.Bus.Timing.Register.0.CBTR0) 3448 0 R (M27.9.18926.tabletitle.Table.22.Baud.rate.prescaler) 3449 0 R
(M27.9.20009.figuretitle.Figure.76.Typical.ResetInterrupt.Vector.Addresses) 3450 0 R (M27.9.21006.figuretitle.Figure59.CAN.Standard.compliant.Bit.Time.Segment.Settings) 3451 0 R (M27.9.22159.sectionxxx.2393.MSCAN08.Power.Down.Mode) 3452 0 R (M27.9.22318.figuretitle.Figure.234..Dual.16Bit.Maskable.Acceptance.Filters) 3453 0 R (M27.9.22424.figuretitle.Figure58.Receive..Transmit.Message.Heading.Standard.Identifier) 3454 0 R
(M27.9.22648.sectionxx.235.Message.Storage) 3455 0 R (M27.9.22819.tablehead.Synchronization.jump.width) 3456 0 R (M27.9.23456.sectionxx.233.Features) 3457 0 R (M27.9.23878.sectionxx.238.Protocol.Violation.Protection) 3458 0 R (M27.9.24306.sectionxx.2314.Programmers.Model.of.Control.Registers) 3459 0 R
(M27.9.24577.section.xxx.532.Receive.Structures) 3460 0 R (M27.9.25544.sectionxx.239.Low.Power.Modes) 3461 0 R (M27.9.25634.section.xxx.572.MSCAN.Module.Control.Register.CMCR) 3462 0 R (M27.9.26601.sectionxx.232.Introduction) 3463 0 R (M27.9.26957.sectionxxx.2392.CPU.Wait.Mode) 3464 0 R
(M27.9.27076.sectionxxx.231413.MSCAN08.Identifier.Mask.Registers.CIDMR03) 3465 0 R (M27.9.27189.section.xxx.574.Programmable.WakeUp.Function) 3466 0 R (M27.9.27322.tabletitle.Table.232..MSCAN08.vs.CPU.operating.modes) 3467 0 R (M27.9.27382.section.xxx.51210.MSCAN08.Identifer.Acceptance.Control.Register.CIDAC) 3468 0 R (M27.9.28169.sectionxxx.2371.Interrupt.Acknowledge) 3469 0 R
(M27.9.28385.tabletitle.Table.21.Synchronization.jump.width) 3470 0 R (M27.9.28465.section.xx.59.Timer.Link) 3471 0 R (M27.9.29185.figuretitle.Figure23.Message.Buffer.Organisation) 3472 0 R (M27.9.30561.figuretitle.Figure.238..Segments.within.the.Bit.Time) 3473 0 R (M27.9.31576.section.xxx.553.Transmit.Structures..User.Model) 3474 0 R
(M27.9.32168.figuretitle.Figure.2314.MSCAN08.Control.Register.Structure) 3475 0 R (M27.9.32467.sectionxxx.231410.MSCAN08.Receive.Error.Counter) 3476 0 R (M27.9.32607.section.xxx.51210.MSCAN08.Identifier.Acceptance.Registers.CIDAR03) 3477 0 R (M27.9.32692.section.xx.510.Clock.System) 3478 0 R (M27.9.33744.sectionxx.234.External.Pins) 3479 0 R
(M27.9.34356.sectionxxx.2392.MSCAN08.Soft.Reset.Mode) 3480 0 R (M27.9.34616.figuretitle.Figure.233..Single.32Bit.Maskable.Identifier.Acceptance.Filter) 3481 0 R (M27.9.35353.CaptionTbl.Table.13.Time.segment.values) 3482 0 R (M27.9.35727.section.xxx.561.Message.Buffer.Outline) 3483 0 R]
>>
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/Limits [(M27.9.36161.sectionxxx.23133.Data.Length.Register.DLR) (M30.9.13397.sectionxx.265.Interrupts)]
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(M27.9.37679.sectionxx.2312.Memory.Map) 3489 0 R (M27.9.38146.section.xxx.562.Data.Segment.Registers.DSR) 3490 0 R (M27.9.39258.sectionxxx.2372.Interrupt.Vectors) 3491 0 R (M27.9.39564.figuretitle.Figure57.Receive..Transmit.Message.Buffer.Extended.Identifier) 3492 0 R (M27.9.40931.section.xx.512.Programmers.Model.of.message.storage) 3493 0 R
(M27.9.41813.sectionxx.239.Low.Power.Modes) 3494 0 R (M27.9.69611.sec1.29.STOP.Mode.low.power.sleep.mode) 3495 0 R (M27.9.96913.Figure.Figure.12.The.ABUS.System) 3496 0 R (M28.9.10678.sectionxx.243.Features) 3497 0 R (M28.9.12619.sectionxxx.2462.Stop.Mode) 3498 0 R
(M28.9.16570.figuretitle.Figure.81.IRQ.Module.Block.Diagram) 3499 0 R (M28.9.18109.sectionxx.245.Keyboard.Initialization) 3500 0 R (M28.9.21307.sectionxx.247.Keyboard.Module.During.Break.Interrupts) 3501 0 R (M28.9.21522.sectionxx.242.Introduction) 3502 0 R (M28.9.21891.bullet..If.the.keyboard.interrupt.is.falling.edge.and.low.levelsensitive.an) 3503 0 R
(M28.9.26376.bullet..Return.of.all.enabled.keyboard.interrupt.pins.to.logic.1.As.long.as) 3504 0 R (M28.9.26667.sectionxxx.2461.Wait.Mode) 3505 0 R (M28.9.27119.sectionxxx.2482.Keyboard.Interrupt.Enable.Register) 3506 0 R (M28.9.29893.sectionxx.248.IO.Registers) 3507 0 R (M28.9.31857.sectionxx.244.Functional.Description) 3508 0 R
(M28.9.36035.sectionxx.246.LowPower.Modes) 3509 0 R (M28.9.53481.sectionxxx.941.Keyboard.Interrupt.Enable.Register.KBIER) 3510 0 R (M28.9.87173.bullet..Vector.fetch.or.software.clear..A.vector.fetch.generates.an) 3511 0 R (M28.9.93958.sectionx.Chapter.24.Keyboard.Module.KBI) 3512 0 R (M28.9.99691.tabletitle.Table.241..IO.Register.Address.Summary) 3513 0 R
(M29.9.11496.sectionxx.252.Introduction) 3514 0 R (M29.9.14911.sectionxx.257.TIMA.During.Break.Interrupts) 3515 0 R (M29.9.15247.sectionxx.254.Functional.Description) 3516 0 R (M29.9.17457.sectionxx.259.IO.Registers) 3517 0 R (M29.9.22303.sectionxx.258.IO.Signals) 3518 0 R
(M29.9.22799.sectionxx.255.Interrupts) 3519 0 R (M29.9.24148.sectionxxx.2542.Input.Capture) 3520 0 R (M29.9.24304.tabletitle.Table.12..Mode.Edge.and.Level.Selection) 3521 0 R (M29.9.24617.sectionxxx.2561.Wait.Mode) 3522 0 R (M29.9.26224.sectionxxx.2541.TIMA.Counter.Prescaler) 3523 0 R
(M29.9.26564.sectionxxx.2582.TIMA.Channel.IO.Pins.PTF3TACH5PTF0TACH2.and.PTE3TACH1PTE2TACH0) 3524 0 R (M29.9.28867.tabletitle.Table.11..Prescaler.Selection) 3525 0 R (M29.9.30151.sectionxxx.1233.Output.Compare) 3526 0 R (M29.9.31139.sectionxxxx.25442.Buffered.PWM.Signal.Generation) 3527 0 R (M29.9.32831.sectionxx.256.LowPower.Modes) 3528 0 R
(M29.9.32927.sectionxx.253.Features) 3529 0 R (M29.9.32956.sectionxxx.2581.TIMA.Clock.Pin.PTD6ATD14TCLK) 3530 0 R (M29.9.33321.sectionxxxx.25441.Unbuffered.PWM.Signal.Generation) 3531 0 R (M29.9.37578.sectionxxx.1281.Timer.Status.and.Control.Register.TSC) 3532 0 R (M29.9.38341.sectionxxx.2593.TIMA.Counter.Modulo.Registers) 3533 0 R
(M29.9.39128.sectionxxx.2592.TIMA.Counter.Registers) 3534 0 R (M29.9.39346.figuretitlewide.Figure.251..TIMA.Block.Diagram) 3535 0 R (M29.9.40223.sectionxxxx.25431.Unbuffered.Output.Compare) 3536 0 R (M29.9.40277.sectionxxxx.25443.PWM.Initialization) 3537 0 R (M29.9.40551.sectionxxxx.25432.Buffered.Output.Compare) 3538 0 R
(M29.9.42415.sectionxxx.1795.TIM.Channel.Registers) 3539 0 R (M29.9.65500.figuretitleindented.Figure.12..PWM.Period.and.Pulse.Width) 3540 0 R (M29.9.68893.figuretitle.Figure.18..CHxMAX.Latency) 3541 0 R (M29.9.69348.sectionxxx.134.Pulse.Width.Modulation.PWM) 3542 0 R (M29.9.73299.sectionxxx.185.Timer.Channel.Status.and.Control.Registers.TSC0TSC3) 3543 0 R
(M29.9.78236.sectionxxx.1762.Stop.Mode) 3544 0 R (M29.9.83118.sectionx.Chapter.25.Timer.Interface.Module.A.TIMA) 3545 0 R (M30.9.12351.sectionxx.262.Introduction) 3546 0 R (M30.9.13397.sectionxx.265.Interrupts) 3547 0 R]
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/Limits [(M30.9.13828.sectionxxx.2671.ADC.Analog.Power.Pin.VDDAREFADC.Voltage.Reference.Pin.VREFH) (M31.9.55859.heading3.Transmitting.a.Message.in.Block.Mode)]
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(M30.9.25500.sectionxxx.2683.ADC.Input.Clock.Register) 3553 0 R (M30.9.25657.sectionxxx.2672.ADC.Analog.Ground.Pin.VSSAADC.Voltage.Reference.Low.Pin.VREFL) 3554 0 R (M30.9.26962.sectionxxx.2641.ADC.Port.IO.Pins) 3555 0 R (M30.9.27483.sectionx.Chapter.26.AnalogtoDigital.Converter.ADC) 3556 0 R (M30.9.31976.sectionxxx.2682.ADC.Data.Register) 3557 0 R
(M30.9.33392.sectionxxx.2642.Voltage.Conversion) 3558 0 R (M30.9.36279.sectionxxx.2662.Stop.Mode) 3559 0 R (M30.9.37919.sectionxx.268.IO.Registers) 3560 0 R (M30.9.39022.sectionxxx.2673.ADC.Voltage.In.ADCVIN) 3561 0 R (M30.9.39691.sectionxxx.2645.Accuracy.and.Precision) 3562 0 R
(M30.9.39856.sectionxx.264.Functional.Description) 3563 0 R (M30.9.40054.sectionxxx.2661.Wait.Mode) 3564 0 R (M30.9.41997.sectionxxx.2643.Conversion.Time) 3565 0 R (M30.9.41998.sectionxx.267.IO.Signals) 3566 0 R (M30.9.42597.sectionxxx.2644.Continuous.Conversion) 3567 0 R
(M30.9.56596.subsection.844..CH3CH0..Channel.Select.Bits.) 3568 0 R (M30.9.61353.tabletitle.Table.92..AD.Clock.Divide.Ratio) 3569 0 R (M30.9.78749.figuretitle.Figure.91..ADC.Block.Diagram) 3570 0 R (M31.8.newlink.51) 3571 0 R (M31.9.10267.heading3.Summary) 3572 0 R
(M31.9.10865.heading1.Functional.Description) 3573 0 R (M31.9.11181.heading1.LowPower.Modes) 3574 0 R (M31.9.11215.figuretitle.Figure.116.J1850.VPW.EOF.and.IFS.Symbols) 3575 0 R (M31.9.11453.heading1.Introduction) 3576 0 R (M31.9.12484.heading3.Performance) 3577 0 R
(M31.9.13555.heading3.BDLC.Stop.Mode) 3578 0 R (M31.9.16209.heading3.Run.Mode) 3579 0 R (M31.9.17051.heading2.J1850.VPW.Symbols) 3580 0 R (M31.9.17064.heading1.BDLC.Protocol.Handler) 3581 0 R (M31.9.19241.heading3.Reset.Mode) 3582 0 R
(M31.9.19359.figuretitle.Figure.117.J1850.VPW.Active.Symbols) 3583 0 R (M31.9.22028.heading2.J1850.VPW.ValidInvalid.Bits.and.Symbols) 3584 0 R (M31.9.22219.sectionxxx.1532.BDLC.CONTROL.REGISTER.2.BTCR2) 3585 0 R (M31.9.25356.heading2.BDLC.Data.Register) 3586 0 R (M31.9.25487.tabletitle.Table.204..BDLC.Transmit.InFrame.Response.Control.Bit.Priority.Encoding) 3587 0 R
(M31.9.25790.figuretitle.Figure.115.J1850.VPW.Passive.Symbols) 3588 0 R (M31.9.26622.heading2.Rx.and.Tx.Shift.Registers) 3589 0 R (M31.9.26754.sectionxxx.2072.J1850.Frame.Format) 3590 0 R (M31.9.27412.heading3.Analog.Loopback.Mode) 3591 0 R (M31.9.28286.heading2.Rx.Digital.Filter) 3592 0 R
(M31.9.28594.heading3.Operation) 3593 0 R (M31.9.29525.heading2.Digital.Loopback.Multiplexer) 3594 0 R (M31.9.30403.figuretitlewide.Figure.202..BDLC.Operating.Modes.State.Diagram) 3595 0 R (M31.9.31730.heading3.BDLC.Wait.Mode) 3596 0 R (M31.9.32008.heading3.Power.Off.Mode) 3597 0 R
(M31.9.33144.sectionx.Chapter.27.Byte.Data.Link.Controller.BDLC) 3598 0 R (M31.9.33595.sectionxxx.1533.BDLC.STATE.VECTOR.REGISTER.BSVR) 3599 0 R (M31.9.34467.heading2.BDLC.Analog.and.Roundtrip.Delay.Register) 3600 0 R (M31.9.34541.heading1.BDLC.CPU.Interface) 3601 0 R (M31.9.35801.heading2.BDLC.Operating.Modes) 3602 0 R
(M31.9.35865.heading2.Protocol.Architecture) 3603 0 R (M31.9.35971.heading1.BDLC.MUX.Interface) 3604 0 R (M31.9.36015.heading3.Digital.Loopback.Mode) 3605 0 R (M31.9.38573.heading1.Features) 3606 0 R (M31.9.40855.heading2.State.Machine) 3607 0 R
(M31.9.41347.tabletitle.Table.205..BDLC.Interrupt.Sources) 3608 0 R (M31.9.46106.figuretitle.Figure.112.BDLC.Rx.Digital.Filter.Block.Diagram) 3609 0 R (M31.9.50837.figuretitle.Figure.1513.BDLC.Protocol.Handler.Outline) 3610 0 R (M31.9.55859.heading3.Transmitting.a.Message.in.Block.Mode) 3611 0 R]
>>
endobj
76 0 obj
<<
/Limits [(M31.9.56212.figuretitle.Figure.114.J1850.VPW.Symbols) (M34.9.82004.tabletitle.Table.5..Vector.Addresses)]
/Names [(M31.9.56212.figuretitle.Figure.114.J1850.VPW.Symbols) 3612 0 R (M31.9.56430.heading3.Receiving.a.Message.in.Block.Mode) 3613 0 R (M31.9.56792.sectionxxx.1564.BDLC.STOP.MODE) 3614 0 R (M31.9.64174.section.77.J1850.MULTIPLEX.BUS.TRANSMITRECEIVE.ERRORS) 3615 0 R (M31.9.65960.figuretitlewide.Figure.201..BDLC.Block.Diagram) 3616 0 R
(M31.9.66581.figuretitle.Figure.118.J1850.VPW.BREAK.Symbols) 3617 0 R (M31.9.71473.tabletitle.Table.202..BDLC.Transceiver.Delay) 3618 0 R (M31.9.76238.tabletitle.Table.203..BDLC.Rate.Selection) 3619 0 R (M31.9.78812.section.76.MESSAGE.ARBITRATION.ON.THE.MULTIPLEX.BUS) 3620 0 R (M31.9.80464.figuretitle.Figure.206..BDLC.Control.Register.2.BCR2) 3621 0 R
(M31.9.82000.figuretitlewide.Figure.2014..J1850.Bus.Message.Format.VPW) 3622 0 R (M31.9.82867.figuretitle.Figure.158.Types.of.InFrame.Response) 3623 0 R (M31.9.90839.sectionxxx.2052.BDLC.Control.Register.1) 3624 0 R (M31.9.95780.sectionxx.326.WAIT.MODE) 3625 0 R (M31.9.95823.sectionxxx.1543.Rx..Tx.SHADOW.REGISTERS) 3626 0 R
(M31.9.96834.heading3.4X.Mode) 3627 0 R (M32.9.13544.heading1.Electrical.Specifications) 3628 0 R (M32.9.15810.heading2.BDLC.Receiver.DC.Electrical.Characteristics) 3629 0 R (M32.9.16572.sectionx.Chapter.28.Electrical.Specifications) 3630 0 R (M32.9.16979.heading2.FLASH.Memory.Characteristics) 3631 0 R
(M32.9.19511.sectionxx.296.Control.Timing) 3632 0 R (M32.9.24465.sectionxxx.762.Component.Specifications) 3633 0 R (M32.9.28565.heading2.BDLC.Receiver.VPW.Symbol.Timings) 3634 0 R (M32.9.29178.sectionxx.293.Functional.Operating.Range) 3635 0 R (M32.9.29179.heading2.EEPROM.Memory.Characteristics) 3636 0 R
(M32.9.30264.figuretitlewide.Figure.292.SPI.Slave.Timing.Diagram) 3637 0 R (M32.9.31128.sectionxx.2912.Timer.Module.Characteristics) 3638 0 R (M32.9.33433.heading2.BDLC.Transmitter.DC.Electrical.Characteristics) 3639 0 R (M32.9.35380.sectionxx.2913.Memory.Characteristics) 3640 0 R (M32.9.40350.figuretitle.Figure.119.SPI.Master.Timing.Diagram) 3641 0 R
(M32.9.40824.sectionxx.294.Thermal.Characteristics) 3642 0 R (M32.9.44493.sectionxx.216.Control.Timing) 3643 0 R (M32.9.53040.figuretitlewide.Figure.211..BDLC.Variable.Pulse.Width.Modulation.VPW.Symbol.Timing) 3644 0 R (M32.9.63795.sectionxx.184.AD.CONVERTOR.CHARACTERISTICS) 3645 0 R (M32.9.64355.sectionxx.212.Maximum.Ratings) 3646 0 R
(M32.9.67354.sectionxx.215.50.Volt.DC.Electrical.Characteristics) 3647 0 R (M32.9.72972.sectionxx.219.CGM.Operating.Conditions) 3648 0 R (M32.9.76310.sectionxx.218.50.Vdc..10.Serial.Peripheral.Interface.SPI.Timing) 3649 0 R (M32.9.79145.sectionxx.2111.CGM.AcquisitionLock.Time.Information) 3650 0 R (M32.9.87248.sectionxx.2116.BDLC.Receiver.VPW.Symbol.Timings) 3651 0 R
(M33.9.14764.heading2.5.Keyboard.Interrupt) 3652 0 R (M33.9.18952.heading2.2.Flash) 3653 0 R (M33.9.27041.sectionxx.12.Introduction) 3654 0 R (M33.9.33419.heading2.4.Config2) 3655 0 R (M33.9.35042.heading2.6.Current.Consumption) 3656 0 R
(M33.9.35666.heading2.8.Monitor.Mode.Entry.and.COP.Disable.Voltage) 3657 0 R (M33.9.46938.heading2.9.LowVoltage.Inhibit.LVI) 3658 0 R (M33.9.56358.heading2.7.Illegal.Address.Reset) 3659 0 R (M33.9.58692.heading2.3.EEPROM) 3660 0 R (M33.9.91889.heading2.1.Specification) 3661 0 R
(M34.9.17151.sectionxx.23.IO.Section) 3662 0 R (M34.9.17571.appendixx.A3.Detailed.Memory.Map.Changes.MC68HC908AS60A.references.have) 3663 0 R (M34.9.19558.figuretitlewide.Figure.22.Control.Status.and.Data.Registers.Sheet.1.of.6) 3664 0 R (M34.9.21579.appendixx.A9.SCI) 3665 0 R (M34.9.23373.heading1.Vector.Addresses.and.Priority) 3666 0 R
(M34.9.24464.figuretitle.Figure.193..ADC.Status.and.Control.Register.ADSCR) 3667 0 R (M34.9.25005.heading1.Additional.Status.and.Control.Registers) 3668 0 R (M34.9.25316.heading1.Ordering.Information) 3669 0 R (M34.9.25728.sectionxx.22.Introduction) 3670 0 R (M34.9.27654.sectionxx.28.Configuration.Register.CONFIG3) 3671 0 R
(M34.9.33053.figuretitlewide.Figure.3..Additional.Status.and.Control.Registers.Sheet.1.of.2) 3672 0 R (M34.9.35023.sectionxx.313.MC.Order.Numbers) 3673 0 R (M34.9.53506.sectionxx.27.Ordering.Information) 3674 0 R (M34.9.82004.tabletitle.Table.5..Vector.Addresses) 3675 0 R]
>>
endobj
77 0 obj
<<
/Limits [(M34.9.82235.appendix.Appendix.A.MC68HC908AZ60E) (M8.9.85498.sectionxxx.142.EPROM.Programming.Sequence)]
/Names [(M34.9.82235.appendix.Appendix.A.MC68HC908AZ60E) 3676 0 R (M34.9.83569.appendixx.A10.MSCAN) 3677 0 R (M5.9.10061.sectionxxx.151.Power.Supply.Pins.VDD.and.VSS) 3678 0 R (M5.9.10106.heading2.BDLCTransmit.Pin.BDTxD) 3679 0 R (M5.9.11809.figuretitlewide.Figure.13..MC68HC08AZxx.Emulator.64Pin.QFP) 3680 0 R
(M5.9.12932.sectionxxx.1510.Port.C.IO.Pins.PTC5PTC0) 3681 0 R (M5.9.16234.sectionxxx.1514.Port.G.IO.Pins.PTG2KBD2PTG0KBD0) 3682 0 R (M5.9.19851.sectionxxx.152.Oscillator.Pins.OSC1.and.OSC2) 3683 0 R (M5.9.19902.sectionxxx.1511.Port.D.IO.Pins.PTD7PTD0ATD8) 3684 0 R (M5.9.21045.sectionxxx.1515.Port.H.IO.Pins.PTH1KBD4PTH0KBD3) 3685 0 R
(M5.9.21770.heading1.Ordering.Information) 3686 0 R (M5.9.24119.sectionxx.13.Features) 3687 0 R (M5.9.25316.heading1.Ordering.Information) 3688 0 R (M5.9.27041.sectionxx.12.Introduction) 3689 0 R (M5.9.27583.sectionxx.14.MCU.Block.Diagram) 3690 0 R
(M5.9.27770.sectionxxx.159.Port.B.IO.Pins.PTB7ATD7PTB0ATD0) 3691 0 R (M5.9.28800.sectionxxx.1513.Port.F.IO.Pins.PTF6PTF0TACH2) 3692 0 R (M5.9.29466.sectionxxx.157.External.Filter.Capacitor.Pin.CGMXFC) 3693 0 R (M5.9.30205.sectionxxx.1512.Port.E.IO.Pins.PTE7SPSCKPTE0TxD) 3694 0 R (M5.9.30283.sectionxxx.1517.CAN.Receive.Pin.CANRxBDLC.Receive.Pin.BDRxD) 3695 0 R
(M5.9.32214.sectionxxx.1516.CAN.Transmit.Pin.CANTxBDLC.Transmit.Pin.BDTxD) 3696 0 R (M5.9.32945.sectionxx.15.Pin.Assignments) 3697 0 R (M5.9.33408.sectionxxx.155.Analog.Power.Supply.Pin.VDDA) 3698 0 R (M5.9.33645.figuretitle.Figure.11..MCU.Block.Diagram.for.the.MC68HC908AZ60A.64Pin.QFP) 3699 0 R (M5.9.34340.heading2.BDLC.Receive.Pin.BDRxD) 3700 0 R
(M5.9.34748.figuretitlewide.Figure.4..MC68HC908AS60A.64Pin.QFP) 3701 0 R (M5.9.34951.sectionxxx.158.Port.A.InputOutput.IO.Pins.PTA7PTA0) 3702 0 R (M5.9.35189.sectionxxx.153.External.Reset.Pin.RST) 3703 0 R (M5.9.38083.heading2.ADC.Analog.Power.Supply.Pin.VDDAREF) 3704 0 R (M5.9.38982.figuretitle.Figure.12..MCU.Block.Diagram.for.the.MC68HC908AS60A.64Pin.QFP.and.52Pin.PLCC) 3705 0 R
(M5.9.39984.figuretitlewide.Figure.5..MC68HC908AS60A.52Pin.PLCC) 3706 0 R (M5.9.41287.sectionxxx.154.External.Interrupt.Pin.IRQ) 3707 0 R (M5.9.41953.sectionxxx.156.Analog.Ground.Pin.VSSA) 3708 0 R (M5.9.52974.heading2.ADC.Reference.High.Voltage.Pin.VREFH) 3709 0 R (M5.9.55481.figuretitle.Figure.16..Power.Supply.Bypassing) 3710 0 R
(M5.9.58159.heading2.ADC.Analog.Ground.Pin.AVSSVREFL) 3711 0 R (M6.9.17151.sectionxx.23.IO.Section) 3712 0 R (M6.9.19558.figuretitlewide.Figure.22.Control.Status.and.Data.Registers.Sheet.1.of.6) 3713 0 R (M6.9.23373.heading1.Vector.Addresses.and.Priority) 3714 0 R (M6.9.25005.heading1.Additional.Status.and.Control.Registers) 3715 0 R
(M6.9.25728.sectionxx.22.Introduction) 3716 0 R (M6.9.33053.figuretitlewide.Figure.3..Additional.Status.and.Control.Registers.Sheet.1.of.2) 3717 0 R (M6.9.58393.figuretitle.Figure.21..Memory.Map.Sheet.1.of.3) 3718 0 R (M6.9.82004.tabletitle.Table.5..Vector.Addresses) 3719 0 R (M7.9.30376.sectionxx.33.Functional.Description) 3720 0 R
(M7.9.38645.sectionxx.32.Introduction) 3721 0 R (M8.9.10670.sectionxx.410.FLASH2.Block.Protect.Register) 3722 0 R (M8.9.13627.heading1.LowPower.Modes) 3723 0 R (M8.9.18317.heading1.Functional.Description) 3724 0 R (M8.9.26430.heading1.FLASH1.Mass.Erase.Operation) 3725 0 R
(M8.9.27037.heading2.FLASH1.Control.Register) 3726 0 R (M8.9.27495.heading2.WAIT.Mode) 3727 0 R (M8.9.28841.heading2.STOP.Mode) 3728 0 R (M8.9.29058.heading2.FLASH1.Block.Protect.Register) 3729 0 R (M8.9.31169.figuretitlewide.Figure.4..FLASH.Programming.Algorithm.Flowchart) 3730 0 R
(M8.9.33276.heading1.Introduction) 3731 0 R (M8.9.34314.sectionxx.48.FLASH.Block.Protection) 3732 0 R (M8.9.35811.heading1.FLASH1.Block.Protection) 3733 0 R (M8.9.39402.heading1.FLASH.ProgramRead.Operation) 3734 0 R (M8.9.39693.sectionxx.42.EPROM.Control.Register.EPMCR) 3735 0 R
(M8.9.60077.sectionxx.45.Charge.Pump.Frequency.Control) 3736 0 R (M8.9.76449.sectionxx.49.FLASH.Block.Protect.Register.FLBPR) 3737 0 R (M8.9.80957.heading1.FLASH1.Page.Erase.Operation) 3738 0 R (M8.9.85498.sectionxxx.142.EPROM.Programming.Sequence) 3739 0 R]
>>
endobj
78 0 obj
<<
/Limits [(M8.9.94293.heading1.Future.EEPROM.Memory) (P.139)]
/Names [(M8.9.94293.heading1.Future.EEPROM.Memory) 3740 0 R (M9.9.10670.sectionxx.410.FLASH2.Block.Protect.Register) 3741 0 R (M9.9.13627.heading1.LowPower.Modes) 3742 0 R (M9.9.27495.heading2.WAIT.Mode) 3743 0 R (M9.9.28841.heading2.STOP.Mode) 3744 0 R
(M9.9.31169.figuretitlewide.Figure.4..FLASH.Programming.Algorithm.Flowchart) 3745 0 R (M9.9.32705.heading1.FLASH2.Block.Protection) 3746 0 R (M9.9.33276.heading1.Introduction) 3747 0 R (M9.9.34314.sectionxx.48.FLASH.Block.Protection) 3748 0 R (M9.9.39402.heading1.FLASH.ProgramRead.Operation) 3749 0 R
(M9.9.42362.heading1.FLASH2.Page.Erase.Operation) 3750 0 R (M9.9.60077.sectionxx.45.Charge.Pump.Frequency.Control) 3751 0 R (M9.9.66798.heading1.FLASH2.Mass.Erase.Operation) 3752 0 R (M9.9.76449.sectionxx.49.FLASH.Block.Protect.Register.FLBPR) 3753 0 R (M9.9.82606.heading2.FLASH2.Control.Register) 3754 0 R
(M9.9.85498.sectionxxx.142.EPROM.Programming.Sequence) 3755 0 R (M9.9.87017.heading1.FLASH2.Control.and.Block.Protect.Registers) 3756 0 R (M9.9.88810.heading2.FLASH2.Block.Protect.Register) 3757 0 R (M9.9.91313.heading1.Functional.Description) 3758 0 R (P.1) 3759 0 R
(P.10) 3760 0 R (P.100) 3761 0 R (P.101) 3762 0 R (P.102) 3763 0 R (P.103) 3764 0 R
(P.104) 3765 0 R (P.105) 3766 0 R (P.106) 3767 0 R (P.107) 3768 0 R (P.108) 3769 0 R
(P.109) 3770 0 R (P.11) 3771 0 R (P.110) 3772 0 R (P.111) 3773 0 R (P.112) 3774 0 R
(P.113) 3775 0 R (P.114) 3776 0 R (P.115) 3777 0 R (P.116) 3778 0 R (P.117) 3779 0 R
(P.118) 3780 0 R (P.119) 3781 0 R (P.12) 3782 0 R (P.120) 3783 0 R (P.121) 3784 0 R
(P.122) 3785 0 R (P.123) 3786 0 R (P.124) 3787 0 R (P.125) 3788 0 R (P.126) 3789 0 R
(P.127) 3790 0 R (P.128) 3791 0 R (P.129) 3792 0 R (P.13) 3793 0 R (P.130) 3794 0 R
(P.131) 3795 0 R (P.132) 3796 0 R (P.133) 3797 0 R (P.134) 3798 0 R (P.135) 3799 0 R
(P.136) 3800 0 R (P.137) 3801 0 R (P.138) 3802 0 R (P.139) 3803 0 R]
>>
endobj
79 0 obj
<<
/Limits [(P.14) (P.197)]
/Names [(P.14) 3804 0 R (P.140) 3805 0 R (P.141) 3806 0 R (P.142) 3807 0 R (P.143) 3808 0 R
(P.144) 3809 0 R (P.145) 3810 0 R (P.146) 3811 0 R (P.147) 3812 0 R (P.148) 3813 0 R
(P.149) 3814 0 R (P.15) 3815 0 R (P.150) 3816 0 R (P.151) 3817 0 R (P.152) 3818 0 R
(P.153) 3819 0 R (P.154) 3820 0 R (P.155) 3821 0 R (P.156) 3822 0 R (P.157) 3823 0 R
(P.158) 3824 0 R (P.159) 3825 0 R (P.16) 3826 0 R (P.160) 3827 0 R (P.161) 3828 0 R
(P.162) 3829 0 R (P.163) 3830 0 R (P.164) 3831 0 R (P.165) 3832 0 R (P.166) 3833 0 R
(P.167) 3834 0 R (P.168) 3835 0 R (P.169) 3836 0 R (P.17) 3837 0 R (P.170) 3838 0 R
(P.171) 3839 0 R (P.172) 3840 0 R (P.173) 3841 0 R (P.174) 3842 0 R (P.175) 3843 0 R
(P.176) 3844 0 R (P.177) 3845 0 R (P.178) 3846 0 R (P.179) 3847 0 R (P.18) 3848 0 R
(P.180) 3849 0 R (P.181) 3850 0 R (P.182) 3851 0 R (P.183) 3852 0 R (P.184) 3853 0 R
(P.185) 3854 0 R (P.186) 3855 0 R (P.187) 3856 0 R (P.188) 3857 0 R (P.189) 3858 0 R
(P.19) 3859 0 R (P.190) 3860 0 R (P.191) 3861 0 R (P.192) 3862 0 R (P.193) 3863 0 R
(P.194) 3864 0 R (P.195) 3865 0 R (P.196) 3866 0 R (P.197) 3867 0 R]
>>
endobj
80 0 obj
<<
/Limits [(P.198) (P.254)]
/Names [(P.198) 3868 0 R (P.199) 3869 0 R (P.2) 3870 0 R (P.20) 3871 0 R (P.200) 3872 0 R
(P.201) 3873 0 R (P.202) 3874 0 R (P.203) 3875 0 R (P.204) 3876 0 R (P.205) 3877 0 R
(P.206) 3878 0 R (P.207) 3879 0 R (P.208) 3880 0 R (P.209) 3881 0 R (P.21) 3882 0 R
(P.210) 3883 0 R (P.211) 3884 0 R (P.212) 3885 0 R (P.213) 3886 0 R (P.214) 3887 0 R
(P.215) 3888 0 R (P.216) 3889 0 R (P.217) 3890 0 R (P.218) 3891 0 R (P.219) 3892 0 R
(P.22) 3893 0 R (P.220) 3894 0 R (P.221) 3895 0 R (P.222) 3896 0 R (P.223) 3897 0 R
(P.224) 3898 0 R (P.225) 3899 0 R (P.226) 3900 0 R (P.227) 3901 0 R (P.228) 3902 0 R
(P.229) 3903 0 R (P.23) 3904 0 R (P.230) 3905 0 R (P.231) 3906 0 R (P.232) 3907 0 R
(P.233) 3908 0 R (P.234) 3909 0 R (P.235) 3910 0 R (P.236) 3911 0 R (P.237) 3912 0 R
(P.238) 3913 0 R (P.239) 3914 0 R (P.24) 3915 0 R (P.240) 3916 0 R (P.241) 3917 0 R
(P.242) 3918 0 R (P.243) 3919 0 R (P.244) 3920 0 R (P.245) 3921 0 R (P.246) 3922 0 R
(P.247) 3923 0 R (P.248) 3924 0 R (P.249) 3925 0 R (P.25) 3926 0 R (P.250) 3927 0 R
(P.251) 3928 0 R (P.252) 3929 0 R (P.253) 3930 0 R (P.254) 3931 0 R]
>>
endobj
81 0 obj
<<
/Limits [(P.255) (P.311)]
/Names [(P.255) 3932 0 R (P.256) 3933 0 R (P.257) 3934 0 R (P.258) 3935 0 R (P.259) 3936 0 R
(P.26) 3937 0 R (P.260) 3938 0 R (P.261) 3939 0 R (P.262) 3940 0 R (P.263) 3941 0 R
(P.264) 3942 0 R (P.265) 3943 0 R (P.266) 3944 0 R (P.267) 3945 0 R (P.268) 3946 0 R
(P.269) 3947 0 R (P.27) 3948 0 R (P.270) 3949 0 R (P.271) 3950 0 R (P.272) 3951 0 R
(P.273) 3952 0 R (P.274) 3953 0 R (P.275) 3954 0 R (P.276) 3955 0 R (P.277) 3956 0 R
(P.278) 3957 0 R (P.279) 3958 0 R (P.28) 3959 0 R (P.280) 3960 0 R (P.281) 3961 0 R
(P.282) 3962 0 R (P.283) 3963 0 R (P.284) 3964 0 R (P.285) 3965 0 R (P.286) 3966 0 R
(P.287) 3967 0 R (P.288) 3968 0 R (P.289) 3969 0 R (P.29) 3970 0 R (P.290) 3971 0 R
(P.291) 3972 0 R (P.292) 3973 0 R (P.293) 3974 0 R (P.294) 3975 0 R (P.295) 3976 0 R
(P.296) 3977 0 R (P.297) 3978 0 R (P.298) 3979 0 R (P.299) 3980 0 R (P.3) 3981 0 R
(P.30) 3982 0 R (P.300) 3983 0 R (P.301) 3984 0 R (P.302) 3985 0 R (P.303) 3986 0 R
(P.304) 3987 0 R (P.305) 3988 0 R (P.306) 3989 0 R (P.307) 3990 0 R (P.308) 3991 0 R
(P.309) 3992 0 R (P.31) 3993 0 R (P.310) 3994 0 R (P.311) 3995 0 R]
>>
endobj
82 0 obj
<<
/Limits [(P.312) (P.37)]
/Names [(P.312) 3996 0 R (P.313) 3997 0 R (P.314) 3998 0 R (P.315) 3999 0 R (P.316) 4000 0 R
(P.317) 4001 0 R (P.318) 4002 0 R (P.319) 4003 0 R (P.32) 4004 0 R (P.320) 4005 0 R
(P.321) 4006 0 R (P.322) 4007 0 R (P.323) 4008 0 R (P.324) 4009 0 R (P.325) 4010 0 R
(P.326) 4011 0 R (P.327) 4012 0 R (P.328) 4013 0 R (P.329) 4014 0 R (P.33) 4015 0 R
(P.330) 4016 0 R (P.331) 4017 0 R (P.332) 4018 0 R (P.333) 4019 0 R (P.334) 4020 0 R
(P.335) 4021 0 R (P.336) 4022 0 R (P.337) 4023 0 R (P.338) 4024 0 R (P.339) 4025 0 R
(P.34) 4026 0 R (P.340) 4027 0 R (P.341) 4028 0 R (P.342) 4029 0 R (P.343) 4030 0 R
(P.344) 4031 0 R (P.345) 4032 0 R (P.346) 4033 0 R (P.347) 4034 0 R (P.348) 4035 0 R
(P.349) 4036 0 R (P.35) 4037 0 R (P.350) 4038 0 R (P.351) 4039 0 R (P.352) 4040 0 R
(P.353) 4041 0 R (P.354) 4042 0 R (P.355) 4043 0 R (P.356) 4044 0 R (P.357) 4045 0 R
(P.358) 4046 0 R (P.359) 4047 0 R (P.36) 4048 0 R (P.360) 4049 0 R (P.361) 4050 0 R
(P.362) 4051 0 R (P.363) 4052 0 R (P.364) 4053 0 R (P.365) 4054 0 R (P.366) 4055 0 R
(P.367) 4056 0 R (P.368) 4057 0 R (P.369) 4058 0 R (P.37) 4059 0 R]
>>
endobj
83 0 obj
<<
/Limits [(P.370) (P.54)]
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